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marvell. moving forward faster doc. no. mv-s105540-00, rev. -- march 4, 2009 document classification: proprietary information 88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver
document conventions note: provides related information or information of special importance. caution: indicates potential damage to hardware or software, or loss of data. warning: indicates a risk of personal injury. document status advance information this document contains design s pecifications for initial product development. specifications may change without notice. contact marvell field application engineers for more information. preliminary information this document contains preliminary data, and a revisi on of this document will be published at a later date. specifications may change without notice. contact marvell field application engineers for more information. final information this document contains specifications on a product that is in final releas e. specifications may change without notice. contact marvell field application engineers for more information. doc status: advance technical publications: 1.00 for more information, visit our website at: www.marvell.com disclaimer no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including phot ocopying and recording, for any purpose, without the express written permission of marvell. marvell retains the right to make changes to this document at any time, with out notice. marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the impli ed warranties of merchantability or fitness for any particular purpose. further, marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situati on if any such products failed. do not use marvell products in these types of equipment or applications. with respect to the products described herein, the user or recipient, in the absence of appropriate u.s. government authorizati on, agrees: 1) not to re-export or release any such information consisting of technology, software or source code controlled for national s ecurity reasons by the u.s. export control regulations ("ear"), to a national of ear country groups d:1 or e:2; 2) not to export the direct product of such technology or such software, to ear country groups d:1 or e:2, if such technology o r software and direct products thereof are controlled for national security reasons by the ear; and, 3) in the case of technology controlled for national security reasons under the ear where the direct product of the technology is a complete plant or component of a plant, not to export to ear country groups d:1 or e:2 the direct product of the plant or major component thereof, if such direct produ ct is controlled for national security reasons by the ear, or is subject to controls under the u.s. munitions list ("usml"). at all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this doc ument in connection with their receipt of any such information. copyright ? 2009. marvell international ltd. all rights reserved . marvell, the marvell logo, moving forward faster, alaska, fas twriter, datacom systems on silicon, libertas, link street, netgx, phyadvantage, prestera, raising the technology bar, the technology within, virtual cable tester, and yukon are registered trademarks of marvell. ants, anyvoltage, discovery, dsp switcher, feroceon, galnet, galt is, horizon, marvell makes it all possible, radlan, unimac, an d vct are trademarks of marvell. all other trademarks are the property of their respective owners. 88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00 rev. -- copyright ? 2009 marvell page 2 document classification: proprietary information march 4, 2009, advance
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classification: proprietary information page 3 o verview the alaska ? ultra 88e1111 gigabit ethernet trans- ceiver is a physical layer device for ethernet 1000base-t, 100base-tx, and 10base-t applica- tions. it is manufactured using standard digital cmos process and contains all the active circuitry required to implement the physical layer functions to transmit and receive data on standard cat 5 unshielded twisted pair. the 88e1111 device incorporates the marvell virtual cable tester ? (vct?) feature, which uses time domain reflectometry (tdr) technology for the remote identification of potential cable malfunctions, thus reducing equipment returns and service calls. using vct, the alaska 88e1111 device detects and reports potential cabling issues such as pair swaps, pair polar- ity and excessive pair skew. the device will also detect cable opens, shorts or any impedance mismatch in the cable and report accurately within one meter the dis- tance to the fault. the 88e1111 device s upports the gigabit media inde- pendent interface (gmii), reduced gmii (rgmii), serial gigabit media indepe ndent interface (sgmii), the ten-bit interface (tbi), and reduced tbi (rtbi) for direct connection to a mac/switch port. the 88e1111 device incorporates an optional 1.25 ghz serdes (serializer/deserializer). the serial interface may be connected directly to a fiber-optic transceiver for 1000base-t/1000base-x m edia conversi on appli- cations. additionally, the 88e1111 device may be used to implement 1000base-t gigabit interface converter (gbic) or small form factor pluggable (sfp) modules. the 88e1111 device uses advanced mixed-signal pro- cessing to perform equaliz ation, echo and crosstalk cancellation, data recovery, and error correction at a gigabit per second data rate. the device achieves robust performance in noisy environments with very low power dissipation. the 88e1111 device is offered in three different pack- age options including a 117-pin tfbga, a 96-pin bcc featuring a body size of only 9 x 9 mm, and a 128 pqfp package. f eatures ? 10/100/1000base-t ieee 802.3 compliant ? supports gmii, tbi, reduced pin count gmii (rgmii), reduced pin count tbi (rtbi), and serial gmii (sgmii) interfaces ? integrated 1.25 ghz serdes for 1000base-x fiber applications ? four rgmii timing modes ? energy detect and energy detect+ low power modes ? three loopback modes for diagnostics ? ?downshift? mode for two-pair cable installations ? fully integrated digital adaptive equalizers, echo cancellers, and crosstalk cancellers ? advanced digital baseline wander correction ? automatic mdi/mdix crosso ver at all speeds of operation ? automatic polarity correction ? ieee 802.3u compliant auto-negotiation ? software programmable led modes including led testing ? automatic detection of fiber or copper operation ? supports ieee 1149.1 jtag ? two-wire serial interface (twsi) and mdc/mdio ? crc checker, packet counter ? packet generation ? virtual cable tester (vct) ? auto-calibration for mac interface outputs ? requires only two supplies: 2.5v and 1.0v (with 1.2v option for the 1.0v supply) ? i/os are 3.3v tolerant ? low power dissipation pave = 0.75w ? 117-pin tfbga, 96-pin bcc, and 128 pqfp package options ? 117-pin tfbga and 96-pin bcc packages avail- able in commercial or industrial grade ? rohs 6/6 compliant packages available
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 4 document classification: proprietary information march 4, 2009, advance 88e1111 device used in copper application 88e1111 device used in fiber application 88e1111 rgmii/gmii mac to sgmii mac conversion m a g n e t i c s mac interface options - gmii/mii - tbi - rgmii - rtbi - sgmii - serial interface media types: - 10base-t - 100base-tx - 1000base-t rj-45 10/100/1000 mbps ethernet mac 88e1111 device serial interface mac interface options - gmii/mii - rgmii media types: - 1000base-x fiber optics 10/100/1000 mbps ethernet mac 88e1111 device serial interface - 4-pin sgmiii mac interface options - gmii - rgmii 3-speed sfp gigabit ethernet mac 88e1111 device (effective sgmii mac)
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classification: proprietary information page 5 table of contents 1.1 117-pin tfbga package................................................................................................6 1.2 96-pin bcc package .....................................................................................................7 1.3 128-pin pqfp package ..................................................................................................8 1.4 pin description ............................................................................................................. ..9 1.4.1 pin type definitions...................................................................................................... ...... 9 1.5 i/o state at various test or reset modes ..................................................................33 1.6 117-pin tfbga pin assignment list - al phabetical by signal name .....................34 1.7 96-pin bcc pin assignment li st - alphabetical by signal name............................36 1.8 128-pin pqfp pin assignment list - al phabetical by signal name........................38 2.1 117-pin tfbga package..............................................................................................40 2.2 96-pin bcc package - top vi ew ............. ................. ................ ............. ............. .........42 2.3 96-pin bcc package - bottom view ...........................................................................43 2.4 128-pin pqfp package ................................................................................................44 3.1 ordering part numbers and package markings........................................................45 3.1.1 rohs 5/6 compliant marking examples .......... ................................................................ 46 3.1.2 rohs 6/6 compliant marking examples .......... ................................................................ 49
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 6 document classification: proprieta ry information march 4, 2009, advance section 1. signal description the 88e1111 device is a 10/100/1000base- t/1000base-x gigabit ethernet transceiver. 1.1 117-pin tfbga package figure 1: 88e1111 device 117-pin tfbga package (top view) figure 2: pin a1 location 123456789 a rxd5 rxd6 s_in+ s_in- s_clk+ s_clk- s_out+ s_out- led_ link1000 a b rx_dv rxd0 rxd3 vddo crs col avdd led_ link100 vddoh b c rx_clk vddo rxd2 rxd4 rxd7 dvdd dvdd led_ link10 led_rx c d tx_clk rx_er rxd1 vss vss vss dvdd config[0] led_tx d e tx_en gtx_clk dvdd vss vss vss dvdd led_ duplex config[1] e f txd0 tx_er dvdd vss vss vss vddoh config[2] config[4] f g nc txd1 txd2 vss vss vss config[3] config[6] config[5] g h txd4 txd3 txd5 vss vss vss vssc sel_ freq xtal1 h j txd6 txd7 dvdd vss vss vss dvdd vddoh xtal2 j k vddo 125clk resetn vss vss vss nc tdo vddox k l intn vddox mdc coma vss vss tdi tms tck l m mdio rset avdd avdd hsdac+ hsdac- avdd avdd trstn m n mdi[0]+ mdi[0]- mdi[1]+ mdi[1]- avdd mdi[2]+ mdi[2]- mdi[3]+ mdi[3]- n 123456789 pin a1 location 88e1111-bab
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 7 signal description 96-pin bcc package 1.2 96-pin bcc package figure 3: 88e1111 device 96-pin bcc package (top view) rx_clk rx_er tx_clk vddo dvdd tx_er gtx_clk tx_en dvdd txd0 txd1 nc txd2 dvdd txd3 txd4 txd5 txd6 mdio intn vddo txd7 125clk vddox mdc coma resetn mdi[0]+ rset mdi[0]- avdd mdi[1]+ mdi[1]- avdd avdd hsdac+ hsdac- mdi[2]+ avdd mdi[2]- mdi[3]+ mdi[3]- tdi avdd tms trstn vddox tck tdo vddoh vssc xtal2 xtal1 sel_ freq dvdd config[6] config[5] config[4] config[3] dvdd config[2] config[1] config[0] vddoh dvdd led_tx led_rx led_dupl ex dvdd vddoh led_link 1000 vddo rxd0 rx_dv rxd2 rxd1 rxd3 rxd4 rxd5 rxd6 dvdd col s_in- s_clk+ s_out+ s_out- led_link 100 vddo rxd7 crs s_in+ s_clk- avdd led_link 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 38 40 37 39 42 44 46 48 41 43 45 47 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 nc dvdd 88e1111 - caa 0 vss
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 8 document classification: proprieta ry information march 4, 2009, advance 1.3 128-pin pqfp package figure 4: 88e1111 device 128-pin pqfp package (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 88e1111 - rcj top view 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 vss avdd vss s_out+ vss s_clk- s_clk+ vss s_in- s_in+ col crs vss dvdd dvdd vss rxd7 rxd6 vddo rxd5 rxd4 rxd3 rxd2 vss rxd1 avdd vss mdi[3]- mdi[3]+ vss avdd vss mdi[2]- mdi[2]+ vss hsdac- hsdac+ avdd vss nc avdd vss mdi[1]- mdi[1]+ vss avdd vss mdi[0]- mdi[0]+ vss rset vss vss led_link10 led_link100 led_link1000 vddoh dvdd led_duplex vss vss led_rx led_tx dvdd vddoh config[0] config[1] config[2] dvdd vss vss config[3] config[4] config[5] config[6] dvdd sel_freq xtal1 xtal2 vssc vddoh tdo vddox tck tms trstn tdi vss vss vss dvdd rxd0 rx_dv vddo dvdd rx_clk rx_er vss tx_clk vddo dvdd tx_er gtx_clk vss tx_en dvdd txd0 txd1 txd2 vss vss dvdd txd3 txd4 txd5 dvdd txd6 txd7 vddo 125clk intn mdio vddox mdc resetn coma vss s_out-
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 9 signal description pin description 1.4 pin description 1.4.1 pin type definitions pin type definition h input with hysteresis i/o input and output i input only o output only pu internal pull up pd internal pull down d open drain output z tri-state output ma dc sink capability
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 10 document classification: proprieta ry information march 4, 2009, advance table 1: media dependent interface 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description n1 n2 29 31 41 42 mdi[0]+ mdi[0]- i/o, d media dependent interface[0]. in 1000base-t mode in mdi configuration, mdi[0] correspond to bi_da. in mdix configuration, mdi[0] correspond to bi_db. in 100base-tx and 10 base-t modes in mdi configuration, mdi[0] are used for the transmit pair. in mdix configuration, mdi[0] are used for the receive pair. mdi[0] should be tied to ground if not used. n3 n4 33 34 46 47 mdi[1]+ mdi[1]- i/o, d media dependent interface[1]. in 1000base-t mode in mdi configuration, mdi[1] correspond to bi_db. in mdix configuration, mdi[1] correspond to bi_da. in 100base-tx and 10 base-t modes in mdi configuration, mdi[1] are used for the receive pair. in mdix configuration, mdi[1] are used for the transmit pair. mdi[1] should be tied to ground if not used.
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 11 signal description pin description n6 n7 39 41 56 57 mdi[2]+ mdi[2]- i/o, d media dependent interface[2]. in 1000base-t mode in mdi configuration, mdi[2] correspond to bi_dc. in mdix configuration, mdi[2] corresponds to bi_dd. in 100base-tx and 10base-t modes, mdi[2] are not used. mdi[2] should be tied to ground if not used. n8 n9 42 43 61 62 mdi[3]+ mdi[3]- i/o, d media dependent interface[3]. in 1000base-t mode in mdi configuration, mdi[3] correspond to bi_dd. in mdix configuration, mdi[3] correspond to bi_dc. in 100base-tx and 10base-t modes, mdi[3] are not used. mdi[3] should be tied to ground if not used. table 1: media dependent interface (continued) 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 12 document classification: proprieta ry information march 4, 2009, advance the gmii interface supports both 1000base-t and 1000base- x modes of operation. the gmii interface pins are also used for the tbi interface. see ta b l e 3 for tbi pin definitions. the mac interface pins are 3.3v tolerant. table 2: gmii/mii interfaces 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description e2 8 14 gtx_clk i gmii transmit clock. gtx_clk provides a 125 mhz clock reference for tx_en, tx_er, and txd[7:0]. this clock can be stopped when the device is in 10/100base- t modes, and also during auto-negotiation. d1 4 10 tx_clk o, z mii transmit clock. tx_clk provides a 25 mhz clock reference for tx_en, tx_er, and txd[3:0] in 100base-tx mode, and a 2.5 mhz clock reference in 10base-t mode. tx_clk provides a 25 mhz, 2.5 mhz, or 0 mhz clock during 1000 mbps good link, auto-negotiation, and link lost states depending on the setting of register 20.6:4. the 2.5 mhz clock is the default rate, which may be programmed to another frequency by writing to register 20.6:4. e1 9 16 tx_en i gmii and mii transmit enable. in gmii/mii mode when tx_en is asserted, data on txd[7:0] along with tx_er is encoded and transmitted onto the cable. tx_en is synchronous to gtx_clk, and synchronous to tx_clk in 100base-tx and 10base-t modes. f2 7 13 tx_er i gmii and mii transmit error. in gmii/mii mode when tx_er and tx_en are both asserted, the transmit error symbol is trans- mitted onto the cable. when tx_er is asserted with tx_en de-asserted, carrier extension symbol is transmitted onto the cable. tx_er is synchronous to gtx_clk, and synchronous to tx_clk in 100base-tx and 10base-t modes.
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 13 signal description pin description j2 j1 h3 h1 h2 g3 g2 f1 20 19 18 17 16 14 12 11 29 28 26 25 24 20 19 18 txd[7] txd[6] txd[5] txd[4] txd[3]/txd[3] txd[2]/txd[2] txd[1]/txd[1] txd[0]/txd[0] i gmii and mii transmit data. in gmii mode, txd[7:0] present the data byte to be trans- mitted onto the cable in 1000base-t mode. in mii mode, txd[3:0] present the data nib- ble to be transmitted onto the cable in 100base-tx and 10base-t modes. txd[7:4] are ignored in these modes, but should be driven either high or low. these pins must not float. txd[7:0] are synchronous to gtx_clk, and synchronous to tx_clk in 100base-tx and 10base-t modes. inputs txd[7:4] should be tied low if not used (e.g., rgmii mode). c1 2 7 rx_clk o, z gmii and mii receive clock. rx_clk pro- vides a 125 mhz clock reference for rx_dv, rx_er, and rxd[7:0] in 1000base-t mode, a 25 mhz clock reference in 100base-tx mode, and a 2.5 mhz clock reference in 10base-t mode. tx_tclk comes from the rx_clk pins used in jitter testing. refer to register 9 for jitter test modes. b1 94 4 rx_dv o, z gmii and mii receive data valid. when rx_dv is asserted, data received on the cable is decoded and presented on rxd[7:0] and rx_er. rx_dv is synchronous to rx_clk. d2 3 8 rx_er o, z gmii and mii receive error. when rx_er and rx_dv are both asserted, the signals indicate an error symbol is detected on the cable. when rx_er is asserted with rx_dv de- asserted, a false carrier or carrier extension symbol is detected on the cable. rx_er is synchronous to rx_clk. table 2: gmii/mii interfaces (continued) 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 14 document classification: proprieta ry information march 4, 2009, advance c5 a2 a1 c4 b3 c3 d3 b2 86 87 89 90 91 93 92 95 120 121 123 124 125 126 128 3 rxd[7] rxd[6] rxd[5] rxd[4] rxd[3]/rxd[3] rxd[2]/rxd[2] rxd[1]/rxd[1] rxd[0]/rxd[0] o, z gmii and mii receive data. symbols received on the cable are decoded and pre- sented on rxd[7:0] in 1000base-t mode. in mii mode, rxd[3:0] are used in 100base-tx and 10bas e-t modes. in mii mode, rxd[7:4] are driven low. rxd[7:0] is synchronous to rx_clk. b5 84 115 crs o, z gmii and mii carrier sense. crs asserts when the receive medium is non-idle. in half- duplex mode, crs is also asserted during transmission. crs assertion during half- duplex transmit can be disabled by program- ming register 16.11 to 0. crs is asynchronous to rx_clk, gtx_clk, and tx_clk. b6 83 114 col o, z gmii and mii collision. in 10/100/ 1000base-t full-duplex modes, col is always low. in 10/100/1000base-t half- duplex modes, col asserts only when both the transmit and receive media are non-idle. in 10base-t half-duplex mode, col is asserted to indicate signal quality error (sqe). sqe can be disabled by clearing reg- ister 16.2 to zero. col is asynchronous to rx_clk, gtx_clk, and tx_clk. table 2: gmii/mii interfaces (continued) 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 15 signal description pin description the tbi interface supports 1000base-t mode of operation. the tbi interface uses the same pins as the gmii interface. the mac interface pins are 3.3v tolerant. table 3: tbi interface 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description e2 8 14 gtx_clk/ tbi_txclk i tbi transmit clock. in tbi mode, gtx_clk is used as tbi_txclk. tbi_txclk is a 125 mhz transmit clock. tbi_txclk provides a 125 mhz clock refer- ence for tx_en, tx_er, and txd[7:0]. d1 4 10 tx_clk/rclk1 o, z tbi 62.5 mhz receive clock- even code group. in tbi mode, tx_clk is used as rclk1. j2 j1 h3 h1 h2 g3 g2 f1 20 19 18 17 16 14 12 11 29 28 26 25 24 20 19 18 txd[7] txd[6] txd[5] txd[4] txd[3] txd[2] txd[1] txd[0] i tbi transmit data. txd[7:0] presents the data byte to be transmitted onto the cable. txd[9:0] are synchronous to gtx_clk. inputs txd[7:4] should be tied low if not used (e.g., rtbi mode). e1 9 16 tx_en/ txd8 i tbi transmit data. in tbi mode, tx_en is used as txd8. txd[9:0] are synchronous to gtx_clk. f2 7 13 tx_er/ txd9 i tbi transmit data. in tbi mode, tx_er is used as txd9. txd[9:0] are synchronous to gtx_clk. tx_er should be tied low if not used (e.g., rtbi mode). c1 2 7 rx_clk/ rclk0 o, z tbi 62.5 mhz receive clock- odd code group. in the tbi mode, rx_clk is used as rclk0. c5 a2 a1 c4 b3 c3 d3 b2 86 87 89 90 91 93 92 95 120 121 123 124 125 126 128 3 rxd[7] rxd[6] rxd[5] rxd[4] rxd[3] rxd[2] rxd[1] rxd[0] o, z tbi receive data code group [7:0]. in the tbi mode, rxd[7:0] present the data byte to be transmitted to the mac. symbols received on the cable are decoded and pre- sented on rxd[7:0]. rxd[7:0] are synchronous to rclk0 and rclk1. b1 94 4 rx_dv/ rxd8 o, z tbi receive data code group bit 8. in the tbi mode, rx_dv is used as rxd8. rxd[9:0] are synchronous to rclk0 and rclk1.
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 16 document classification: proprieta ry information march 4, 2009, advance d2 3 8 rx_er/ rxd9 o, z tbi receive data code group bit 9. in the tbi mode, rx_er is used as rxd9. rxd[9:0] are synchronous to rclk0 and rclk1. b5 84 115 crs/ comma o, z tbi valid comma detect. in the tbi mode, crs is used as comma. b6 83 114 col/lpbk i tbi mode loopback. in the tbi mode, col is used to indicate loopback on the tbi. when a ?0 - 1" transition is sampled on this pin, bit 0.14 is set to 1. when a ?1 - 0" is sampled on this pin, bit 0.14 is reset to 0. if this feature is not used, the col pin should be driven low on the board. this pin should not be left floating in tbi mode. table 3: tbi interface (continued) 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 17 signal description pin description the rgmii interface sup ports 10/100/1000base- t and 1000base-x modes of oper ation.the rgmii interface pins are also used for the rtbi interface. see ta b l e 5 for rtbi pin definitions. th e mac interface pins are 3.3v tolerant. table 4: rgmii interface 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description e2 8 14 gtx_clk/ txc i rgmii transmit clock provides a 125 mhz, 25 mhz, or 2.5 mhz reference clock with 50 ppm tolerance depending on speed. in rgmii mode, gtx_clk is used as txc. h2 g3 g2 f1 16 14 12 11 24 20 19 18 txd[3]/td[3] txd[2]/td[2] txd[1]/td[1] txd[0]/td[0] i rgmii transmit data. in rgmii mode, txd[3:0] are used as td[3:0]. in rgmii mode, txd[3:0] run at double data rate with bits [3:0] presented on the rising edge of gtx_clk, and bits [7:4] presented on the falling edge of gtx_clk. in this mode, txd[7:4] are ignored. in rgmii 10/100base-t modes, the trans- mit data nibble is presented on txd[3:0] on the rising edge of gtx_clk. e1 9 16 tx_en/ tx_ctl i rgmii transmit control. in rgmii mode, tx_en is used as tx _ctl. tx_en is pre- sented on the rising edge of gtx_clk. a logical derivative of tx_en and tx_er is presented on the falling edge of gtx_clk. c1 2 7 rx_clk/ rxc o, z rgmii receive clock provides a 125 mhz, 25 mhz, or 2.5 mhz reference clock with 50 ppm tolerance derived from the received data stream depending on speed. in rgmii mode, rx_clk is used as rxc. b1 94 4 rx_dv/ rx_ctl o, z rgmii receive control. in rgmii mode, rx_dv is used as rx_ctl. rx_dv is pre- sented on the rising edge of rx_clk. a logical derivative of rx_dv and rx_er is presented on the falling edge of rx_clk. b3 c3 d3 b2 91 93 92 95 125 126 128 3 rxd[3]/rd[3] rxd[2]/rd[2] rxd[1]/rd[1] rxd[0]/rd[0] o, z rgmii receive data. in rgmii mode, rxd[3:0] are used as rd[3:0]. in rgmii mode, rxd[3:0] run at double data rate with bits [3:0] presented on the rising edge of rx_clk, and bits [7:4] presented on the fall- ing edge of rx_clk. in this mode, rxd[7:4] are ignored. in rgmii 10/100base-t modes, the receive data nibble is presented on rxd[3:0] on the rising edge of rx_clk. rxd[3:0] are synchronous to rx_clk.
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 18 document classification: proprieta ry information march 4, 2009, advance the rtbi interface supports 1000base-t mode of operation. the rtbi inte rface uses the same pins as the rgmii interface. the mac interf ace pins are 3.3v tolerant. table 5: rtbi interface 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description e2 8 14 gtx _ clk/ txc i rgmii transmit clock provides a 125 mhz reference clock with 50 ppm tolerance. in rtbi mode, gtx_clk is used as txc. h2 g3 g2 f1 16 14 12 11 24 20 19 18 txd[3]/td[3] txd[2]/td[2] txd[1]/td[1] txd[0]/td[0] i rtbi transmit data. in rtbi mode, txd[3:0] are used as td[3:0]. td[3:0] run at double data rate with bits [3:0] presented on the rising edge of gtx_clk, and bits [8:5] presented on the falling edge of gtx_clk. in this mode, txd[7:4] are ignored. e1 9 16 tx_en/ td4_td9 irtbi transmit data. in rtbi mode, tx_en is used as td4_td9. td4_td9 runs at a double data rate with bit 4 presented on the rising edge of gtx_clk, and bit 9 presented on the falling edge of gtx_clk. c1 2 7 rx_clk/ rxc o, z rtbi receive clock provides a 125 mhz ref- erence clock with 50 ppm tolerance derived from the received data stream. in rtbi mode, rx_clk is used as rxc. b3 c3 d3 b2 91 93 92 95 125 126 128 3 rxd[3]/rd[3] rxd[2]/rd[2] rxd[1]/rd[1] rxd[0]/rd[0] o, z rtbi receive data. in rtbi mode, rxd[3:0] are used as rd[3:0]. rd[3:0] runs at double data rate with bits [3:0] presented on the rising edge of rx_clk, and bits [8:5] presented on the fall- ing edge of rx_clk. in this mode, rxd[7:4] are ignored. b1 94 4 rx_dv/ rd4_rd9 o, z rtbi receive data. in rtbi mode, rx_dv is used as rd4_rd9. rd4_rd9 runs at a double data rate with bit 4 presented on the rising edge of rx_clk, and bit 9 presented on the fall- ing edge of rx_clk.
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 19 signal description pin description table 6: sgmii interface 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description a3 a4 82 81 113 112 s_in+ s_in- i sgmii transmit data. 1.25 gbaud input - positive and negative. input impedance on the s_in pins may be programmed for 50 ohm or 75 ohm imped- ance by setting register 26.6. the input impedance default setting is determined by the 75/50 ohm configuration pin. a5 a6 79 80 110 109 s_clk+ s_clk- i/o sgmii 625 mhz receive clock. for serial interface modes (hwcfg_mode[3:0] = 1x00) the s_clk pins become signal detect (sd) inputs. a7 a8 77 75 107 105 s_out+ s_out- o, z sgmii receive data. 1.25 gbaud output - positive and negative. output impedance on the s_out pins may be programmed for 50 ohm or 75 ohm impedance by setting register 26.5. output amplitude can be adjusted via register 26.2:0. the output impedance default setting is determined by the 75/50 ohm configura- tion pin.
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 20 document classification: proprieta ry information march 4, 2009, advance table 7: 1.25 ghz serial high speed interface 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description a3 a4 82 81 113 112 s_in+ s_in- i 1.25 ghz input - positive and negative. when this interface is used as a mac inter- face, the mac transmitter?s positive output connects to the s_in+. the mac transmit- ter?s negative output connects to the s_in-. when this interface is used as a fiber inter- face, the fiber-optic transceiver?s positive output connects to the s_in+. the fiber-optic transceiver?s negative output connects to the s_in-. input impedance on the s_in pins may be programmed for 50 ohm or 75 ohm imped- ance by setting register 26.6. the input impedance default setting is determined by the 75/50 ohm configuration pin. a5 a6 79 80 110 109 s_clk+/sd+ s_clk-/sd- i signal detect input. for serial interface modes the s_clk pins become signal detect (sd) inputs. a7 a8 77 75 107 105 s_out+ s_out- o, z 1.25 ghz output ? positive and negative. when this interface is used as a mac inter- face, s_out+ connects to the mac receiver?s positive input. s_out- connects to the mac receiver?s negative input. when this interface is used as a fiber inter- face, s_out+ connects to the fiber-optic transceiver?s positive input. s_out- con- nects to the fiber-optic transceiver?s negative input. output impedance on the s_out pins may be programmed for 50 ohm or 75 ohm impedance by setting register 26.5. output amplitude can be adjusted via register 26.2:0. the output impedance default setting is determined by the 75/50 ohm configura- tion pin. b3 91 125 rxd[3] o, z serial mac interface copper link status[1] connection. 1 = copper link up 0 = copper link down
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 21 signal description pin description c3 93 126 rxd[2] o, z serial mac interface copper link status[0] connection. 1 = copper link down 0 = copper link up d3 92 128 rxd[1] o, z serial mac interface phy_sigdet[1] con- nection. 1 = s_out valid code groups according to clause 36. 0 = s_out invalid b2 95 3 rxd[0] o, z serial mac interface phy_sigdet[0] con- nection. 1 = s_out invalid 0 = s_out valid code groups according to clause 36 table 7: 1.25 ghz serial high speed interface (continued) 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 22 document classification: proprieta ry information march 4, 2009, advance table 8: management interface and interrupt 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description l3 25 35 mdc i 3.3v to l e r a n t mdc is the management data clock refer- ence for the serial management interface. a continuous clock stream is not expected. the maximum frequency supported is 8.3 mhz. m1 24 33 mdio i/o 3.3v to l e r a n t mdio is the management data. mdio transfers management data in and out of the device synchronously to mdc. this pin requires a pull-up resistor in a range from 1.5 kohm to 10 kohm. l1 23 32 intn d the polarity of the intn pin may be pro- grammed at hardware reset by setting the int_pol bit. polarity: 0 = active high 1 = active low table 9: two-wire serial interface 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description l3 25 35 mdc/scl i two-wire serial interface (twsi) serial clock line. when the 88e1111 device is con- nected to the bus, mdc connects to the serial clock line (scl). data is input on the rising edge of scl, and output on the falling edge. m1 24 33 mdio/sda i/o twsi serial data line. when the 88e1111 device is connected to the bus, mdio con- nects to the serial data line (sda). this pin is open-drain and may be wire-ored with any number of open-drain devices.
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 23 signal description pin description table 10: led interface 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description c8 76 100 led_link10 o, ma parallel led output for 10base-t link or speed. this active low led pin may be pro- grammed in direct drive or combined led modes by programming register led_link control register 24.4:3. in direct drive led mode, this pin indicates 10 mbps link up or down. in combined led mode, the output from led_link10, led_link100, and led_link1000 must be read together to determine link and speed status. led_link10 is a multi-function pin used to configure the 88e1111 device at the de- assertion of hardware reset. b8 74 99 led_link100 o, ma parallel led output for 100base-tx link or speed. this active low led pin may be pro- grammed in direct drive or combined led modes by programming register led_link control register 24.4:3. in direct drive led mode, this pin indicates 100 mbps link up or down. in combined led mode, the output from led_link10, led_link100, and led_link1000 must be read together to determine link and speed status. led_link100 is a multi-function pin used to configure the 88e1111 device at the de- assertion of hardware reset. a9 73 98 led_link1000 o, ma parallel led output for 1000base-t link/ speed or link indicator. this active low led pin may be programmed in direct drive or combined led modes by programming reg- ister led_link control register 24.4:3. in direct drive led mode, this pin indicates 1000 mbps link up or down. in combined led mode, the output from led_link1000 indicates link status. led_link1000 is a multi-function pin used to configure the 88e1111 device at the de- assertion of hardware reset.
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 24 document classification: proprieta ry information march 4, 2009, advance e8 70 95 led_duplex o, ma parallel led duplex or duplex/collision modes. the led_duplex pin may be pro- grammed to mode 1 or mode 2 by setting register bit 24.2. mode 1 low = full-duplex high = half-duplex blink = collision mode 2 low = full-duplex high = half-duplex mode 3 low = fiber link up high = fiber link down led_duplex is a multi-function pin used to configure the 88e1111 device at the de- assertion of hardware reset. table 10: led interface (continued) 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 25 signal description pin description c9 69 92 led_rx o, ma parallel led receive activity or receive activity/link modes. led_rx may be pro- grammed to mode 1 or mode 2 by setting register bit 24.1. mode 1 low = receiving high = not receiving mode 2 low = link up high = link down blink = receiving led_rx is a multi-function pin used to con- figure the 88e1111 device at the de-asser- tion of hardware reset. d9 68 91 led_tx o, ma parallel led transmit activity or rx/tx activity/link modes. led_tx may be pro- grammed to mode 1 or mode 2 by setting register bit 24.0. mode 1 low = transmitting high = not transmitting mode 2 low = link up high = link down blink = transmitting or receiving led_tx is a multi-function pin used to con- figure the 88e1111 device at the de-asser- tion of hardware reset. table 10: led interface (continued) 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 26 document classification: proprieta ry information march 4, 2009, advance table 11: jtag interface 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin type pin name description l7 44 67 tdi i, pu boundary scan test data input. tdi contains an internal 150 kohm pull-up resistor. l8 46 69 tms i, pu boundary scan test mode select input. tms contains an internal 150 kohm pull-up resistor. l9 49 70 tck i, pu boundary scan test clock input. tck contains an internal 150 kohm pull-up resistor. m9 47 68 trstn i, pu boundary scan test reset input. active low. trstn contains an internal 150 kohm pull- up resistor as per the 1149.1 specification. after power up, the jtag state machine should be reset by applying a low signal on this pin, or by keeping tms high and apply- ing 5 tck pulses, or by pulling this pin low by a 4.7 kohm resistor. k8 50 72 tdo o, z boundary scan test data output.
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 27 signal description pin description table 12: clock/configuration/reset/i/o 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description k2 22 31 125clk o clock 125. a generic 125 mhz clock refer- ence generated for use on the mac device. this output can be disabled via dis_125 through the config[3] pin. d8 65 88 config[0] i config[0] pin configures phy_adr[2:0] bits of the physical address. each led pin is hardwired to a constant value. the values associated to the con- fig[0] pin are latched at the de-assertion of hardware reset. config[0] pin must be tied to one of the pins based on the configuration options selected. they should not be left floating. for the two-wire serial interface (twsi) device address, the lower 5 bits, which are phyadr[4:0], are latched during hardware reset, and the device address bits [6:5] are fixed at ?10?. e9 64 87 config[1] i config[1] pin configures phy_adr[4:3] and ena_pause options. each led pin is hardwired to a constant value. the values associated to the con- fig[1] pin are latched at the de-assertion of hardware reset. config[1] pin must be tied to one of the pins based on the configuration options selected. they should not be left floating. for the twsi device address, the lower 5 bits, which are phyadr[4:0], are latched during hardware reset, and the device address bits [6:5] are fixed at ?10?. f8 63 86 config[2] i config[2] pin configures aneg[3:1] bits. each led pin is hardwired to a constant value. the values associated to the con- fig[2] pin are latched at the de-assertion of hardware reset. config[2] pin must be tied to one of the pins based on the configuration options selected. they should not be left floating.
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 28 document classification: proprieta ry information march 4, 2009, advance g7 61 82 config[3] i config[3] pin configures aneg[0], ena_xc, and dis_125 options. each led pin is hardwired to a constant value. the values associated to the con- fig[3] pin are latched at the de-assertion of hardware reset. config[3] pin must be tied to one of the pins based on the configuration options selected. they should not be left floating. f9 60 81 config[4] i config [4] pin configures hwcfg_mode[2:0] options. g9 59 80 config[5] i config[5] pin configures dis_fc, dis_sleep, and hwcfg_mode[3] options. g8 58 79 config[6] i config[6] pin configures sel_twsi, int_pol, and 75/50 ohm options. h8 56 77 sel_freq frequency selection for xtal1 input nc = selects 25 mhz clock input. tied low = selects 125 mhz clock input. internally divided to 25 mhz. sel_freq is internally pulled up. h9 55 76 xtal1 i reference clock. 25 mhz 50 ppm or 125 mhz 50 ppm oscillator input. pll clocks are not recommended. j9 54 75 xtal2 0 reference clock. 25 mhz 50 ppm toler- ance crystal reference. when the xtal2 pin is not connected, it should be left floating. there is no option for a 125 mhz crystal. see ?crystal oscillator? application note for details. table 12: clock/configuration/reset/i/o (continued) 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 29 signal description pin description k3 28 36 resetn i hardware reset. active low. xtal1 must be active for a minimum of 10 clock cycles before the rising edge of resetn. resetn must be pulled high for normal operation. l4 27 37 coma i coma disables all active circuitry to draw absolute minimum power. the coma power mode can be activated by asserting high on the coma pin. to deactivate the coma power mode, tie the coma pin low. upon deactivating coma mode, the 88e1111 device will continue normal operation. the coma power mode cannot be enabled as long as hardware reset is enabled. in coma mode, the phy cannot wake up on its own by detecting activity on the cat 5 cable. table 12: clock/configuration/reset/i/o (continued) 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 30 document classification: proprieta ry information march 4, 2009, advance table 13: test 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description m5 m6 37 38 53 54 hsdac+ hsdac- analog pd test pins. these pins should be left floating but brought out for probing. table 14: control and reference 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description m2 30 39 rset analog i constant voltage reference. external 5.0 kohm 1% resistor connection to vss required for each pin.
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 31 signal description pin description table 15: power & ground 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description b7 m3 m4 m7 m8 n5 32 35 36 40 45 78 44 49 52 59 64 104 avdd power analog power. 2.5v. c6 c7 d7 e3 e7 f3 j3 j7 1 6 10 15 57 62 67 71 85 2 6 12 17 23 27 78 85 90 96 117 118 dvdd power digital power. 1.0v (instead of 1.0v, 1.2v can be used). b9 f7 j8 52 66 72 73 89 97 vddoh power 2.5v power supply for led and config pins. k9 l2 26 48 34 71 vddox power 2.5v supply for the mdc/mdio, intn, 125clk, resetn, jtag pin power. b4 c2 k1 5 21 88 96 5 11 30 122 vddo power 2.5v i/o supply for the mac interface pins.
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 32 document classification: proprieta ry information march 4, 2009, advance d4 d5 d6 e4 e5 e6 f4 f5 f6 g4 g5 g6 h4 h5 h6 j4 j5 j6 k4 k5 k6 l5 l6 01 9 15 21 22 38 40 43 45 48 51 55 58 60 63 65 66 83 84 93 94 101 102 103 106 108 111 116 119 127 vss gnd global ground h7 53 74 vssc gnd ground reference for xtal1 and xtal2 pins. this pin must be connected to the ground. g1 k7 13 51 50 nc nc no connect. do not connect these pins to anything table 15: power & ground (continued) 117-tfbga pin # 96-bcc pin # 128-pqfp pin # pin name pin type description
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 33 signal description i/o state at various test or reset modes 1.5 i/o state at various test or reset modes pin(s) isolate loopback or normal operation software reset hardware reset power down coma power down and isolate mdi[3:0] active active tri-state tri- state tri-state tri-state tri-state tx_clk tri-state active reg. 16.3 state 0 = low 1 = active low reg. 16.3 state 0 = low 1 = active reg. 16.3 state 0 = low 0 = static but can be either high or low tri-state rxd[0], rxd[2] tri-state active high high high high tri-state rxd[7:3,1], rx_dv, rx_er, crs tri-state active low low low low tri-state col tri-state tbi mode - input else -active tri-state tri-state tbi mode - input else - low tbi mode - input else - low tri-state rx_clk tri-state active reg. 16.3 state 0 = low 1 = active low reg. 16.3 state 0 = low 1 = active reg. 16.3 state 0 = low 0 = static but can be either high or low tri-state s_clk s_out active active tri-state tri-state reg. 16.3 state 0 = tri-state 1 = active tri-state active mdio active active active tri-state active tri-state active int active active tri-state tri-state tri-state tri-state tri-state led_*** active active high high high high high tdo tri-state tri-state tri-state tr i-state tri-state active tri-state 125clk reg. 16.4 state 0 = toggle 1 = low reg. 16.4 state 0 = toggle 1 = low reg. 16.4 state 0 = toggle 1 = low toggle reg. 16.4 state 0 = toggle 1 = low reg. 16.3 state 0 = static but can be either high or low 0 = low reg. 16.4 state 0 = toggle 1 = low
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 34 document classification: proprieta ry information march 4, 2009, advance 1.6 117-pin tfbga pin assignment list - alphabetical by signal name pin # pin name pin # pin name k2 125clk a9 led_link1000 b7 avdd c9 led_rx m3 avdd d9 led_tx m4 avdd l3 mdc m7 avdd n2 mdi[0]- m8 avdd n1 mdi[0]+ n5 avdd n4 mdi[1]- b6 col n3 mdi[1]+ l4 coma n7 mdi[2]- d8 config[0] n6 mdi[2]+ e9 config[1] n9 mdi[3]- f8 config[2] n8 mdi[3]+ g7 config[3] m1 mdio f9 config[4] g1 nc g9 config[5] k7 nc g8 config[6] k3 resetn b5 crs m2 rset c6 dvdd b2 rxd0 c7 dvdd d3 rxd1 d7 dvdd c3 rxd2 e3 dvdd b3 rxd3 e7 dvdd c4 rxd4 f3 dvdd a1 rxd5 j3 dvdd a2 rxd6 j7 dvdd c5 rxd7 e2 gtx_clk c1 rx_clk m6 hsdac- b1 rx_dv m5 hsdac+ d2 rx_er l1 intn a6 s_clk- e8 led_duplex a5 s_clk+ c8 led_link10 a4 s_in- b8 led_link100 a3 s_in+
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 35 signal description 117-pin tfbga pin assignment list - alphabetical by signal name a8 s_out- d4 vss a7 s_out+ d5 vss h8 sel_freq d6 vss l9 tck e4 vss l7 tdi e5 vss k8 tdo e6 vss l8 tms f4 vss m9 trstn f5 vss f1 txd0 f6 vss g2 txd1 g4 vss g3 txd2 g5 vss h2 txd3 g6 vss h1 txd4 h4 vss h3 txd5 h5 vss j1 txd6 h6 vss j2 txd7 j4 vss d1 tx_clk j5 vss e1 tx_en j6 vss f2 tx_er k4 vss b4 vddo k5 vss c2 vddo k6 vss k1 vddo l5 vss b9 vddoh l6 vss f7 vddoh h7 vssc j8 vddoh h9 xtal1 k9 vddox j9 xtal2 l2 vddox 1.6 117-pin tfbga pin assignment list - alphabetical by signal name (continued) pin # pin name pin # pin name
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 36 document classification: proprieta ry information march 4, 2009, advance 1.7 96-pin bcc pin assignment list - alphabetical by signal name pin # pin name pin # pin name 22 125clk 74 led_link100 32 avdd 73 led_link1000 35 avdd 69 led_rx 36 avdd 68 led_tx 40 avdd 25 mdc 45 avdd 31 mdi[0]- 78 avdd 29 mdi[0]+ 83 col 34 mdi[1]- 27 coma 33 mdi[1]+ 65 config[0] 41 mdi[2]- 64 config[1] 39 mdi[2]+ 63 config[2] 43 mdi[3]- 61 config[3] 42 mdi[3]+ 60 config[4] 24 mdio 59 config[5] 13 nc 58 config[6] 51 nc 84 crs 28 resetn 1dvdd 30rset 6dvdd 95rxd0 10 dvdd 92 rxd1 15 dvdd 93 rxd2 57 dvdd 91 rxd3 62 dvdd 90 rxd4 67 dvdd 89 rxd5 71 dvdd 87 rxd6 85 dvdd 86 rxd7 8 gtx_clk 2 rx_clk 38 hsdac- 94 rx_dv 37 hsdac+ 3 rx_er 23 intn 80 s_clk- 70 led_duplex 79 s_clk+ 76 led_link10 81 s_in-
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 37 signal description 96-pin bcc pin assignment list - alphabetical by signal name 82 s_in+ 4 tx_clk 75 s_out- 9 tx_en 77 s_out+ 7 tx_er 56 sel_freq 5 vddo 49 tck 21 vddo 44 tdi 88 vddo 50 tdo 96 vddo 46 tms 52 vddoh 47 trstn 66 vddoh 11 txd0 72 vddoh 12 txd1 26 vddox 14 txd2 48 vddox 16 txd3 0 vss 17 txd4 53 vssc 18 txd5 55 xtal1 19 txd6 54 xtal2 20 txd7 1.7 96-pin bcc pin assignment list - alphabetical by signal name (continued) pin # pin name pin # pin name
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 38 document classification: proprieta ry information march 4, 2009, advance 1.8 128-pin pqfp pin assignment list - alphabetical by signal name pin # pin name pin # pin name 31 125clk 32 intn 44 avdd 95 led_duplex 49 avdd 100 led_link10 52 avdd 99 led_link100 59 avdd 98 led_link1000 64 avdd 92 led_rx 104 avdd 91 led_tx 114 col 35 mdc 37 coma 41 mdi[0]+ 88 config[0] 42 mdi[0]- 87 config[1] 46 mdi[1]+ 86 config[2] 47 mdi[1]- 82 config[3] 56 mdi[2]+ 81 config[4] 57 mdi[2]- 80 config[5] 61 mdi[3]+ 79 config[6] 62 mdi[3]- 115 crs 33 mdio 2dvdd 50nc 6 dvdd 36 resetn 12 dvdd 39 rset 17 dvdd 7 rx_clk 23 dvdd 4 rx_dv 27 dvdd 8 rx_er 78 dvdd 3 rxd0 85 dvdd 128 rxd1 90 dvdd 126 rxd2 96 dvdd 125 rxd3 117 dvdd 124 rxd4 118 dvdd 123 rxd5 14 gtx_clk 121 rxd6 53 hsdac+ 120 rxd7 54 hsdac- 110 s_clk+
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 39 signal description 128-pin pqfp pin assignment list - alphabetical by signal name 109 s_clk- 9 vss 113 s_in+ 15 vss 112 s_in- 21 vss 107 s_out+ 22 vss 105 s_out- 38 vss 77 sel_freq 40 vss 70 tck 43 vss 67 tdi 45 vss 72 tdo 48 vss 69 tms 51 vss 68 trstn 55 vss 10 tx_clk 58 vss 16 tx_en 60 vss 13 tx_er 63 vss 18 txd0 65 vss 19 txd1 66 vss 20 txd2 83 vss 24 txd3 84 vss 25 txd4 93 vss 26 txd5 94 vss 28 txd6 101 vss 29 txd7 102 vss 5 vddo 103 vss 11 vddo 106 vss 30 vddo 108 vss 122 vddo 111 vss 73 vddoh 116 vss 89 vddoh 119 vss 97 vddoh 127 vss 34 vddox 74 vssc 71 vddox 76 xtal1 1 vss 75 xtal2 1.8 128-pin pqfp pin assignment list - alphabetical by signal name (continued) pin # pin name pin # pin name
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 40 document classification: proprieta ry information march 4, 2009, advance section 2. package mechanical dimensions 2.1 117-pin tfbga package (all dimensions in mm.)
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 41 package mechanical dimensions 117-pin tfbga package table 16: 117-pin tfbga package dimensions dimensions in mm symbol min nom max a----1.54 a1 0.40 0.50 0.60 a2 0.84 0.89 0.94 c 0.32 0.36 0.40 d 9.90 10.00 10.10 e 13.90 14.00 14.10 d1 -- 8.00 -- e1 -- 12.00 -- e--1.00-- b 0.50 0.60 0.70 aaa 0.20 bbb 0.25 ccc 0.35 ddd 0.15 md/me note: 1. controlling dimension: millimeter. 2. primary datum c and seating plane are defined by the spherical crowns of the solder balls. 3. dimension b is measured at the maximum solder ball diameter, parallel to primary datum c.
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 42 document classification: proprieta ry information march 4, 2009, advance 2.2 96-pin bcc package - top view 9.000.10 z y top view 0.15 0.6700.025 0.80 max 0.0750.025 pin 1 corner x 9.000.10 0.20 0.05 1 3 50 51 71 73 24 95 96 74 75 27 49 47 25 23 0.300.05 detail "a" (1x) 0.08 z c0.2 0.08 z x y 0.4000.05 x y m m z z
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 43 package mechanical dimensions 96-pin bcc package - bottom view 2.3 96-pin bcc package - bottom view 0.400.05 cl.(pkg.) ''a'' (pin 1 corner) bottom view 7.200 7.00 8.20 9.00 0.2 0.2 "b" 4.100 0.600 typ. 9.00 8.20 4.800 7.20 5.800 cl.(pkg.) 4.100 0.600 typ. 3.50 0.600.10 0.600.10 3.50 detail "b" (95x) 0.300.05 y x z 0.08 y x z 0.08 m m
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 44 document classification: proprieta ry information march 4, 2009, advance 2.4 128-pin pqfp package 0.5 basic 0.25 min 1.6 nominal 38 39 1 128 64 65 102 103 pin1 indicator 23.20 0.10 17.20 0.20 0.22 0.15 3.40 max
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 45 order information ordering part numbers and package markings section 3. order information 3.1 ordering part numbers and package markings figure 5 shows the ordering part numbering scheme for the 88e1111 devices. contact marvell ? faes or sales representatives for complete ordering information. figure 5: sample part number table 17: 88e1111 part order options - rohs 5/6 compliant package package type part order number 88e1111 117-pin tfbga - commercial 88E1111-XX-BAB-C000 88e1111 117-pin tfbga - industrial 88e1111-xx-bab-i000 88e1111 96-pin bcc - commercial 88e1111-xx-caa-c000 88e1111 96-pin bcc - industrial 88e1111-xx-caa-i000 88e1111 128-pin pqfp - commercial 88e1111-xx-rcj-c000 table 18: 88e1111 part order options - rohs 6/6 compliant package package type part order number 88e1111 117-pin tfbga - commercial 88e1111-xx- bab1c000 88e1111 117-pin tfbga - industrial 88e1111-xx- bab1i000 88e1111 96-pin bcc - commercial 88e1111-xx-caa1c000 88e1111 96-pin bcc - industrial 88e1111-xx-caa1i000 88e1111 128-pin pqfp - commercial 88e1111-xx-rcj1c000 ? xx ? xxx ? cxxx - xxxx part number 88e1111 package code bab = 117-pin tfbga caa = 96-pin bcc rcj - 128-pin pqfp environmental ?-? = rohs 5/6 compliant package 1 = rohs 6/6 compliant package temperature range c = commercial i = industrial custom code custom code (optional) 88e1111 custom code
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 46 document classification: proprieta ry information march 4, 2009, advance 3.1.1 rohs 5/6 compliant marking examples figure 6 is an example of the package marking and pin 1 location for the 88e1111 117-pin tfbga commercial rohs 5/6 compliant package. figure 6: 88e1111 117-pin tfbga commercial rohs 5/6 compliant package marking and pin 1 location figure 7 is an example of the package marking and pin 1 location for the 88e1111 117-pin tfbga industrial rohs 5/6 compliant package. figure 7: 88e1111 117-pin tfbga industrial rohs 5/6 compliant package marking and pin 1 location 88e1111-bab lot number yyww xx@ country country of origin (contained in the mold id or marked as the last line on the package.) pin 1 location n ote : the above example is not drawn to scale. location of markings is approximate. logo part number, package code, environmental code environmental code - no code = rohs 5/6 1 = rohs 6/6 date code, custom code, assembly plant code yyww = date code xx = custom code @ = assembly location code 88e1111-bab lot number yyww xx@ country country of origin (contained in the mold id or marked as the last line on the package.) pin 1 location n ote : the above example is not drawn to scale. location of markings is approximate. i logo part number, package code, environmental code environmental code - no code = rohs 5/6 1 = rohs 6/6 date code, custom code, assembly plant code yyww = date code xx = custom code @ = assembly location code industrial grade package marking
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 47 order information ordering part numbers and package markings figure 8 is an example of the package marking and pin 1 location for the 88e 1111 96-pin bcc commercial rohs 5/6 compliant package. figure 8: 88e1111 96-pin bcc commercial rohs 5/6 compliant package marking and pin 1 location figure 9 is an example of the package marking and pin 1 loca tion for the 88e1111 96-pin bcc industrial rohs 5/ 6 compliant package. figure 9: 88e1111 96-pin bcc industrial rohs 5/6 compliant package marking and pin 1 loca- tion 88e1111-caa lot number yyww xx@ country country of origin (contained in the mold id or marked as the last line on the package.) pin 1 location n ote : the above example is not drawn to scale. location of markings is approximate. part number, package code, environmental code environmental code - no code = rohs 5/6 1 = rohs 6/6 date code, custom code, assembly plant code yyww = date code xx = custom code @ = assembly location code logo 88e1111-caa lot number yyww xx@ country country of origin (contained in the mold id or marked as the last line on the package.) pin 1 location n ote : the above example is not drawn to scale. location of markings is approximate. i logo part number, package code, environmental code environmental code - no code = rohs 5/6 1 = rohs 6/6 date code, custom code, assembly plant code yyww = date code xx = custom code @ = assembly location code industrial grade package marking
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 48 document classification: proprieta ry information march 4, 2009, advance figure 10 is an example of the package marking and pin 1 location for the 88e1111 128-pin pqfp commercial rohs 5/6 compliant package. figure 10: 88e1111 128-pin pqfp commercial rohs 5/6 compliant package marking and pin 1 location 88e1111-rcj lot number yyww xx@ country country of origin (contained in the mold id or marked as the last line on the package.) pin 1 location n ote : the above example is not drawn to scale. location of markings is approximate. part number, package code, environmental code environmental code - no code = rohs 5/6 1 = rohs 6/6 date code, custom code, assembly plant code yyww = date code xx = custom code @ = assembly location code logo
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 49 order information ordering part numbers and package markings 3.1.2 rohs 6/6 compliant marking examples figure 11 is an example of the package marking and pin 1 location for the 88e1111 117-pin tfbga commercial rohs 6/6 compliant package. figure 11: 88e1111 117-pin tfbga commercial rohs 6/6 compliant package marking and pin 1 location figure 12 is an example of the package marking and pin 1 location for the 88e1111 117-pin tfbga industrial rohs 6/6 compliant package. figure 12: 88e1111 117-pin tfbga industrial ro hs 6/6 compliant package marking and pin 1 location 88e1111-bab1 lot number yyww xx@ country country of origin (contained in the mold id or marked as the last line on the package.) pin 1 location n ote : the above example is not drawn to scale. location of markings is approximate. logo part number, package code, environmental code environmental code - no code = rohs 5/6 1 = rohs 6/6 date code, custom code, assembly plant code yyww = date code xx = custom code @ = assembly location code 88e1111-bab1 lot number yyww xx@ country country of origin (contained in the mold id or marked as the last line on the package.) pin 1 location n ote : the above example is not drawn to scale. location of markings is approximate. i logo part number, package code, environmental code environmental code - no code = rohs 5/6 1 = rohs 6/6 date code, custom code, assembly plant code yyww = date code xx = custom code @ = assembly location code industrial grade package marking
88e1111 product brief integrated 10/100/1000 ultra gigabit ethernet transceiver doc. no. mv-s105540-00, rev. -- copyright ? 2009 marvell page 50 document classification: proprieta ry information march 4, 2009, advance figure 13 is an example of the package marking and pin 1 location for the 88e1111 96-pin bcc commercial rohs 6/6 compliant package. figure 13: 88e1111 96-pin bcc commercial ro hs 6/6 compliant package marking and pin 1 location figure 14 is an example of the package marking and pin 1 loca tion for the 88e1111 96-pi n bcc industrial rohs 6/ 6 compliant package. figure 14: 88e1111 96-pin bcc industrial rohs 6/6 compliant package marking and pin 1 loca- tion 88e1111-caa1 lot number yyww xx@ country country of origin (contained in the mold id or marked as the last line on the package.) n ote : the above example is not drawn to scale. location of markings is approximate. pin 1 location logo part number, package code, environmental code environmental code - no code = rohs 5/6 1 = rohs 6/6 date code, custom code, assembly plant code yyww = date code xx = custom code @ = assembly location code 88e1111-caa1 lot number yyww xx@ country country of origin (contained in the mold id or marked as the last line on the package.) n ote : the above example is not drawn to scale. location of markings is approximate. pin 1 location i logo part number, package code, environmental code environmental code - no code = rohs 5/6 1 = rohs 6/6 date code, custom code, assembly plant code yyww = date code xx = custom code @ = assembly location code industrial grade package marking
copyright ? 2009 marvell doc. no. mv-s105540-00, rev. -- march 4, 2009, advance document classifi cation: proprietary information page 51 order information ordering part numbers and package markings figure 15 is an example of the package marking and pin 1 location for the 88e1111 128-pin pqfp commercial rohs 6/6 compliant package. figure 15: 88e1111 128-pin pqfp commercial ro hs 6/6 compliant package marking and pin 1 location 88e1111-rcj1 lot number yyww xx@ country country of origin (contained in the mold id or marked as the last line on the package.) n ote : the above example is not drawn to scale. location of markings is approximate. pin 1 location logo part number, package code, environmental code environmental code - no code = rohs 5/6 1 = rohs 6/6 date code, custom code, assembly plant code yyww = date code xx = custom code @ = assembly location code
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